PQCEmbedded: 工业物联网微控制器、ASIL-D 汽车最高功能安全等级与全栈 PQC 部署

PQCEmbedded 提供超低功耗 RISC-V 专用密码处理器芯片核心、自定义 ISA 硬件指令集扩展以及功耗低于 10mW 的轻量级协处理器，专为电池供电的低功耗物联网 (IoT) 终端与嵌入式微控制器高效执行 FIPS 203 ML-KEM 与 FIPS 204 ML-DSA 标准。

PQCEmbedded RISC-V Core Architecture & Coprocessor Interface

RV32IMCB pipeline, custom PQC vector instructions, and tightly-coupled memory scratchpad

Central System: RISC-V Crypto Core - RV32-PQC Microcontroller

Cryptographic Nodes

  • 32-bit RISC-V Pipeline
  • Custom PQC Vector Unit
  • Tightly-Coupled Scratchpad
  • True Random Generator
  • Physical Memory Guard

Architectural Layers & Protocols

  • RISC-V Architecture Baseline (RV32IMCB (Integer, Multiply, Compressed, Bitmanip)): Delivering general-purpose application execution with minimal silicon footprint (< 25 kGE).
  • Custom Cryptographic ISA Extensions (Custom Opcode Extensions for NTT & Montgomery): Accelerating polynomial vector butterflies and modular reductions directly in the ALU pipeline.
  • Memory Architecture & Scratchpads (Tightly-Coupled SRAM with Zero Latency): Storing polynomial vectors and twiddle tables without cache misses or variable bus delays.
  • Ultra-Low-Power Energy Scheduler (Dynamic Voltage & Frequency Scaling (DVFS)): Operating down to 0.8V supply voltage, drawing less than 8.5 mW during peak cryptographic operations.

Key Metrics: < 8.5 mW (Peak Operating Power) | < 25 kGE (Silicon Gate Count) | RV32IM (RISC-V Base Architecture) | < 180 µs (ML-KEM Keygen Time)

低功耗RISC-V PQC密码加速核心、亚10毫瓦ML-KEM/ML-DSA协处理器与物联网边缘飞地

深入剖析 NIST FIPS 203/204/205 标准、格密码学、侧信道攻击防护及后量子计算防御架构中的Low-Power RISC-V PQC Cryptographic Accelerator Cores, Sub-10mW ML-KEM/ML-DSA Coprocessors & IoT Edge Enclaves关键工程实践。

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications