Core engineering and protocols for Custom RISC-V PQC Extensions.
Standard 32-bit ARM Cortex-M0/M3 and basic RISC-V cores lack vector processing capabilities. Executing ML-KEM polynomial multiplication requires millions of 16-bit multiplications, modular reductions, and memory moves, leading to slow multi-millisecond handshakes that drain IoT batteries.
PQCEmbedded introduces four custom RISC-V instructions: pqc.ntt.bf (evaluating the forward butterfly), pqc.mont.red (single-cycle Montgomery reduction), pqc.shake.round (Keccak theta-rho-pi-chi-iota transformation), and pqc.pack (compressing polynomial coefficients into serialized bytes). These dedicated execution units reduce total cycle count by over 82% while adding less than 6,000 gates of silicon area.