PQCEmbedded: Microcontroladores IoT Industriais, Segurança Automotiva ASIL-D e Pilhas PQC

A PQCEmbedded fornece núcleos de processadores criptográficos RISC-V de ultrabaixo consumo, extensões de instruções ISA personalizadas e coprocessadores de menos de 10 mW projetados para executar FIPS 203 ML-KEM e FIPS 204 ML-DSA em dispositivos IoT alimentados por bateria e microcontroladores embarcados.

PQCEmbedded RISC-V Core Architecture & Coprocessor Interface

RV32IMCB pipeline, custom PQC vector instructions, and tightly-coupled memory scratchpad

Central System: RISC-V Crypto Core - RV32-PQC Microcontroller

Cryptographic Nodes

  • 32-bit RISC-V Pipeline
  • Custom PQC Vector Unit
  • Tightly-Coupled Scratchpad
  • True Random Generator
  • Physical Memory Guard

Architectural Layers & Protocols

  • RISC-V Architecture Baseline (RV32IMCB (Integer, Multiply, Compressed, Bitmanip)): Delivering general-purpose application execution with minimal silicon footprint (< 25 kGE).
  • Custom Cryptographic ISA Extensions (Custom Opcode Extensions for NTT & Montgomery): Accelerating polynomial vector butterflies and modular reductions directly in the ALU pipeline.
  • Memory Architecture & Scratchpads (Tightly-Coupled SRAM with Zero Latency): Storing polynomial vectors and twiddle tables without cache misses or variable bus delays.
  • Ultra-Low-Power Energy Scheduler (Dynamic Voltage & Frequency Scaling (DVFS)): Operating down to 0.8V supply voltage, drawing less than 8.5 mW during peak cryptographic operations.

Key Metrics: < 8.5 mW (Peak Operating Power) | < 25 kGE (Silicon Gate Count) | RV32IM (RISC-V Base Architecture) | < 180 µs (ML-KEM Keygen Time)

Núcleos Aceleradores Criptográficos PQC RISC-V de Baixa Potência, Coprocessadores ML-KEM/ML-DSA Sub-10mW e Enclaves de Borda IoT

Referência técnica de engenharia autoritativa para low-power risc-v pqc cryptographic accelerator cores, sub-10mw ml-kem/ml-dsa coprocessors & iot edge enclaves em normas NIST FIPS 203/204/205, criptografia em reticulados, mitigação de ataques por canal lateral e infraestrutura resistente a computadores quânticos.

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications