PQCEmbedded：産業用IoTマイクロコントローラ、ASIL-D車載機能安全、フルスタックPQC

PQCEmbeddedは、超低消費電力RISC-V暗号プロセッサコア、カスタムISA命令拡張、およびFIPS 203 ML-KEMとFIPS 204 ML-DSAを実行するための10mW未満のコプロセッサを提供し、バッテリー駆動のIoT機器や組込みマイコンを保護します。

PQCEmbedded RISC-V Core Architecture & Coprocessor Interface

RV32IMCB pipeline, custom PQC vector instructions, and tightly-coupled memory scratchpad

Central System: RISC-V Crypto Core - RV32-PQC Microcontroller

Cryptographic Nodes

  • 32-bit RISC-V Pipeline
  • Custom PQC Vector Unit
  • Tightly-Coupled Scratchpad
  • True Random Generator
  • Physical Memory Guard

Architectural Layers & Protocols

  • RISC-V Architecture Baseline (RV32IMCB (Integer, Multiply, Compressed, Bitmanip)): Delivering general-purpose application execution with minimal silicon footprint (< 25 kGE).
  • Custom Cryptographic ISA Extensions (Custom Opcode Extensions for NTT & Montgomery): Accelerating polynomial vector butterflies and modular reductions directly in the ALU pipeline.
  • Memory Architecture & Scratchpads (Tightly-Coupled SRAM with Zero Latency): Storing polynomial vectors and twiddle tables without cache misses or variable bus delays.
  • Ultra-Low-Power Energy Scheduler (Dynamic Voltage & Frequency Scaling (DVFS)): Operating down to 0.8V supply voltage, drawing less than 8.5 mW during peak cryptographic operations.

Key Metrics: < 8.5 mW (Peak Operating Power) | < 25 kGE (Silicon Gate Count) | RV32IM (RISC-V Base Architecture) | < 180 µs (ML-KEM Keygen Time)

低消費電力RISC-V PQC暗号アクセラレータコア、10mW未満のML-KEM/ML-DSAコプロセッサとIoTエッジエンクレーブ

Authoritative technical engineering reference for low-power risc-v pqc cryptographic accelerator cores, sub-10mw ml-kem/ml-dsa coprocessors & iot edge enclaves in NIST FIPS 203/204/205 standards, lattice-based cryptography, side-channel attack mitigation, and quantum-resilient infrastructure.

Core Engineering Areas

Technical Articles

Related Cluster Architecture Specifications