Core engineering and protocols for Tightly-Coupled Memory Architecture.
Data caches improve average software execution speed but introduce variable latency: if a memory access hits L1 cache it executes in 1 cycle, while a cache miss requires 10 to 30 cycles. In microcontrollers executing cryptographic algorithms, this timing discrepancy creates an exploitable cache-timing side channel.
PQCEmbedded abandons traditional data caches in favor of a 32 KB Tightly-Coupled Memory (TCM) mapped directly into the core's address space. The TCM features dual-port single-cycle access: the instruction pipeline and arithmetic coprocessor access polynomial vector coefficients simultaneously without bus arbitration delays or timing variance.